System clocks for electrical devices (e.g., printed circuit boards) may be constrained by a number of error sources. For example, these error sources may include path length discrepancies and mismatch (e.g., for printed circuit board traces), static phase offset of phase-locked loop (PLL)/delay-locked loop (DLL) clocks and zero delay buffers, channel-to-channel skew, and various forms of jitter.
Various approaches to eliminate mismatch between clock channels (e.g., for digital clock systems) include using known layout techniques and providing gate delays and trimming. However, these approaches generally offer only a very coarse approximation and typically do not reduce overall mismatch, especially over process, voltage and temperature. The gate delay approach also has a lower limit of a single delay stage and, although it is possible to modify a stage delay with additional loading for example, this generally does not result in a very linear and controlled process.
Conventional clock generator devices (e.g., clock generator or buffer chips) may use a skew control method based on voltage-controlled oscillator (VCO) stage clocks to generate a coarse skew control to reduce large variations in skew. However, this approach cannot perform very fine variations in skew control as fine variations in skew control generally would require more stages in the VCO, which may slow down the VCO and may also create additional jitter. There is also a lower limit to the fine variation with this approach, based on the VCO stage delay, and the circuitry may be large and complex if many stages are used as the necessary logic increases at a 2N rate (where N is the number of VCO stages). As a result, there is a need for improved clock techniques for providing clock signals.